Capacitive arrays, also called arrays with charge distribution, are routinely used in various applications, for example in analogue to digital converters (ADC). A capacitive array comprises at least two capacitive entities of different values.
FIG. 1 shows an example of capacitive array. The capacitive array 1 comprises a number of capacitive entities (C1, C2, C3, C4, C5). Each capacitive entity (C1, C2, C3, C4, C5) has a first terminal and a second terminal. The first terminals of the capacitive entities (C1, C2, C3, C4, C5) are interlinked. The reference Vc denotes the electrical potential at the first terminals of the capacitive entities (C1, C2, C3, C4, C5). The second terminals of the capacitive entities (C1, C2, C3, C4, C5) are not necessarily interlinked. The second terminal of each capacitive entity Ci may be subject to an associated electrical potential Vi. The electrical potentials Vi may take values that are different from each other.
A parameter determining the operation of a capacitive array is the ratio of the values of the capacitive entities to each other, for example C3/C1. Currently, efforts are directed towards producing capacitive arrays such that the ratio of the values of the capacitive entities has a value as accurate as possible.
Producing capacitive arrays using plate capacitors is known. U.S. Pat. No. 6,111,742 discloses an example of metal-oxide-metal (MOM) plate capacitor.
Plate capacitors are normally quite large in order to be able to adjust the values of the capacitors as much as possible. Because of this, these capacitors have relatively high values. The capacitive entities thus have relatively accurate values.
Furthermore, when fabricating such capacitive arrays, each capacitive entity is integrated in an associated block. A block comprises an area of the surface of a substrate normally dedicated to a given function, in this case a capacitive entity. Each block is located apart from the other blocks, the distance between two blocks being normally imposed by the fabrication constraints. The capacitive array is therefore structured as a number of blocks of equal dimensions. Fabricating such an array from blocks is relatively simple because of this similarity between the blocks.
FIG. 2 is an example of a top-view diagram of two capacitive arrays, each comprising twelve capacitive entities. Each block 3a, 3b, etc. of each capacitive array 1, 2 comprises an associated capacitive entity, Connections 4 interlink the capacitive entities of one and the same capacitive array.
Also known, for example from U.S. Pat. No. 5,208,725, is the production of fringe capacitors. FIG. 3 shows an example of a capacitive entity produced with fringe capacitors, according to the prior art.
A given capacitive entity 5 comprises a first comb 6 and a second comb 7 nested in each other. In FIG. 3, the second comb 7 is double. The value of the capacitive entity is equal to the sum of the values of the fringe capacitors between the teeth of the combs, in the direction X orthogonal to the axis of the teeth of the comb. This type of capacitor has the advantage of occupying less space than a plate capacitor for a given capacitance value.